`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/11/05 18:08:18
// Design Name: 
// Module Name: sixteen_bit_fulladd
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module sixteen_bit_fulladd(A,B,CI,S,CO);
  input [15:0] A,B;
  input CI;
  output [15:0] S;
  output CO; 
  
  wire [2:0] w;
  four_bit_lookforward_fulladd
   F1(A[3:0],B[3:0],CI,S[3:0],w[0]);
  four_bit_lookforward_fulladd
   F2(A[7:4],B[7:4],w[0],S[7:4],w[1]);
  four_bit_lookforward_fulladd
   F3(A[11:8],B[11:8],w[1],S[11:8],w[2]);
  four_bit_lookforward_fulladd
   F4(A[15:12],B[15:12],w[2],S[15:12],CO);
endmodule
